Subject: Workshop on Parallel Programming on the IBM RS/6000 SP

From: [email-masked] (Jeanne C. Butler)
Date: Tue, 20 Aug 1996 11:39:48 -0500

Workshop on Parallel Programming on the IBM RS/6000 SP

Sunday September 29 - Friday October 4, 1996

Cornell Theory Center
Cornell University
Ithaca, NY

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	** Space is still available in this workshop ** 
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The Cornell Theory Center (CTC), a nationally funded high-performance
computing and communications center, is offering a one-week workshop,
including lectures and laboratory sessions, on parallel programming
for the IBM SP. CTC's IBM SP, which consists of 512 RISC processors
connected by a high-performance switch, is the largest of its kind in
the world. The SP programming model is distributed memory.

This workshop will offer sessions on the following topics:

- CTC Essentials:
        What programmers need to know about CTC's IBM SP system
        configuration and administration.

- Using CTC's IBM SP Effectively:
        How to design and code programs that make the best use of the
        IBM SP's features.

- The Message Passing Interface (MPI) Standard Library:
        How to write parallel programs using this message passing
        standard.

- Parallelization Case Study using MPI and
     High Performance Fortran (HPF):
        A step-by-step presentation of converting a serial program to
        a parallel program, and tuning its performance.

All topics will be presented using a mix of lectures and programming
exercises, giving participants hands-on experience with parallel
programming.

A full description of the topics, as well as the preliminary agenda
and registration form, is available online at:
        http://www.tc.cornell.edu/Events/SP.Oct96/

Registrations will continue to be accepted on a space available basis,
until September 3, 1996.

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