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Date: Wed, 25 Nov 1998 09:35:35 +0000
To: CHEMISTRY@www.ccl.net
From: "Rzepa, Henry" <h.rzepa@ic.ac.uk>
Subject: Re: CCL:M:MOPAC97



>Hi again,
>
>	Can anybody tell me where I can get the source code for MOPAC97 or
>MOPAC95?   QCPE only goes upto MOPAC93.
>
>


I believe that  MOPAC97 will only be distributed directly by  Fujitsu, and
not  by QCPE. You should contact a  Fujitsu office or reseller.

Dr Henry Rzepa,  Dept. Chemistry,  Imperial College,  LONDON SW7 2AY;
mailto:rzepa@ic.ac.uk; Tel  (44) 171 594 5774; Fax: (44) 171 594 5804.
URL: http://www.ch.ic.ac.uk/rzepa/
If my digital email signature is invalid, download a new root at
http://www.belsign.be/en/services/receive/install-ca.html

From chemistry-request@www.ccl.net  Wed Nov 25 07:20:28 1998
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Date: Wed, 25 Nov 1998 12:19:43 +0000
To: chemistry@www.ccl.net
From: Darren Andrews <darrena@chemistry.leeds.ac.uk>
Subject: 3D Graphics Accelerators as computational tools


Has anyone thought of using the awesome floating point performance of 3D
graphics accelerators in computational chemistry?  A decent 3D Voodoo II
card is theoretically capable of about 9Gflops/sec, two of them together
give 18Gflops/sec, and with an AGP interface can talk to the cpu at over
500M/sec.  Is it possible to harness this power, and would it even be
worthwhile trying?

Darren Andrews.

PostGraduate Student,
School of Chemistry,
University of Leeds,
Leeds.
LS2 9JT.
England.

Darrena@chem.leeds.ac.uk

Tel: 0113 233 6594.
Fax: 0113 233 6565.

From chemistry-request@www.ccl.net  Wed Nov 25 09:03:01 1998
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Date: Wed, 25 Nov 1998 08:02:42 -0600 (CST)
From: "Kenneth W. Egan" <kegan@austin.ibm.com>
To: Darren Andrews <darrena@chemistry.leeds.ac.uk>
Cc: chemistry@www.ccl.net
Subject: Re: CCL:3D Graphics Accelerators as computational tools
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> Has anyone thought of using the awesome floating point performance of 3D
> graphics accelerators in computational chemistry?  A decent 3D Voodoo II
> card is theoretically capable of about 9Gflops/sec, two of them together
> give 18Gflops/sec, and with an AGP interface can talk to the cpu at over
> 500M/sec.  Is it possible to harness this power, and would it even be
> worthwhile trying?

   This brings up several issues....
   
     1). Do the chips actual implement IEEE floating point, or is it
         proprietary...like 24.8 or 22.10 ( fixed )

     2.) Practical only in Geometry processors. However, to use each
         FP multiplier, as that, requires making sure none of the
         other pipeline units are operative, or at least those
         stages are not interactive.... World scaling, vertex
         transformation, lighting, clipping....etc. The matrices
         are usually hard coded, so initialization may require
         significant setup.

     3.) End result----> must do setup, AGP write to adapter
         then AGP read....max theoritical bandwidth is thus
         250 MFLOPS regardless of the number of FP multipliers
         in the chip. 


     The IBM/motorola Power 630 is capable of 1 FP op/cycle,
     the newest chips can achieve 450 MFLOPS. I think the 
     new IMAC has a 630...not sure.


     Not a bad line of reasoning though.


     Ken Egan
     IBM 3D VLSI design
     Austin

     

